CEN/CENELEC/JTC 22 ‘Quantum Technologies’ publishes its first deliverable: Layer model of Quantum Computing

CEN/CENELEC/JTC 22 ‘Quantum Technologies’ have published their first ever deliverable in the form of a Technical Report (TR). The document covers the universal gate-based quantum-computing model, also known as a digital or circuit quantum-computing model, on multiple physical systems. TR 18202:2025 slices down the overall complexity of quantum computing into two main groups of layers, summarizing theoretical and practical approaches with state-of-the-art definition.

After receiving many European contributions over the past two years, CEN/CENELEC/JTC 22 ‘Quantum Technologies’ (established in 2023) published its deliverable in the Work Programme: ‘Layer model of Quantum Computing’ (CEN/CLC/TR 18202:2025) on 3 September 2025.

The work was led by CEN/CENELEC/JTC 22/WG 3 ‘Quantum Computing and Simulation,’ with written contribution from our CEN Members and CENELEC Members. Furthermore, various industrial partners, experts and academic contributors also provided input, including but not limited to Delft Circuits, TNO, CINI, ParityQC, DLR, QDeepTech, Alice&Bob and Pasqal. The TR is focused on a high-level (functional) description of the ‘layers’ in quantum computing involved where the individual layer definition details are undoubtedly crucial for other future standards.

The scope of the document is restricted to a universal gate-based quantum-computing model, also known as a digital or circuit quantum-computing model, on multiple physical systems, such as transmon, spin-qubit, ion-trap, neutral-atom, and others. This document does not apply to technologies like the universal adiabatic quantum-computing model and its heuristic form quantum annealing if they do not correspond to a gate-based quantum circuit. Due to major architecture differences in lower layers, it does not apply to the universal photonic one-way quantum computing model either, even though it is fully compatible with the gate-based quantum-computing model. Moreover, quantum computing models that are not universal, such as quantum simulators and special purposes, are also out of scope.

Limiting the scope to a universal gate-based quantum computing model is justified by expected commonalities at the higher layers, mainly above the hardware abstraction layer (HAL), up to the service layer. These commonalities imply a market for software products usable for a wide range of quantum computing technologies.

The document defines a ‘layer model’ that covers the entire stack of universal gate-based quantum computers. The group of lower-level (hardware) layers are organized in different hardware stacks tailored to different hardware architectures, while the group of higher-level (software) layers are built on top of these and expected to be common for all quantum computing systems. The higher up in the stack, the more agnostic it will be from underlying layers. Reducing the dependencies between higher and lower layers is a crucial point for optimized quantum computations. A co-requisite point is to allow for a free but well-defined flow of information up and down the higher and lower layers to allow for co-designing hardware and software.

CEN/CLC/TR 18202:2025 is undoubtedly one of the high-level work approaches, triggering individual future standards for the definition of the mentioned different layers for better exchangeability.

More information is available from one of our National Standardization Bodies (listed here for CEN/CLC/TR 18202:2025).

To get involved in further activities and deliverable development in Quantum Technologies, CEN/CENELEC/JTC 22 is inviting you to get in touch!